Final-Level Cache (FLC) Architecture
In current computer operating systems, surprisingly, only a small percentage of application code loaded in main memory is actually active. Most processes are idle, yet in aggregate, they take up a lot of expensive DRAM main memory space. Due to the way these computing systems are architected, the main memory doesn’t know when to load or unload snippets of codes in its applications. Marvell’s Final-Level Cache (FLC™) architecture solves this issue by redefining the main memory hierarchy, automatically loading pieces of code as needed and purging unneeded code, freeing up space for other applications.
Cutting the amount of DRAM main memory needed in a system and replacing it with a small layer of high-speed DRAM cache and an inexpensive solid-state drive (SSD) main memory has the potential to spark the development of lower cost and lower power products. FLC architecture cuts the DRAM needed in a system by as much as a factor of ten, enabling computing systems to use about half the energy they consume today
- Smaller FLC DRAM operates at lower power
- Can be co-located next to the CPU, potentially running faster with lower I/O interface power and reducing overall form factor
- Increases battery life
- Easily flushed out to SSD for complete power-down and fast wake-up
- Provides significant DRAM cost savings, larger for higher-end devices
- Allows inexpensive servers to handle Big Data requiring terabytes of main memory
FLC technology is ideal for almost all computing devices including smartphones, tablets, laptops, servers, wearables, Internet of Things devices, and storage devices. For example, FLC technology can enable the development of the industry’s thinnest, lowest cost ultra book at only half the operating power. It also holds the potential to decrease battery size or increase standby battery life at half the cost of today’s offerings.