Galileo Technology Unveils The GALNET Switching Architecture For Networking

San Jose, California (March 18, 1995) –

Galileo Technology today unveiled its revolutionary GALNET switching architecture for networking products and introduced its first member, the GT-48001 Switched Ethernet Controller. The GALNET architecture is revolutionary in its simplicity, its cost-performance, its adherence to standards, and its expandability. Its main objective is to enable the creation of low cost, state-of-the-art network switches for workgroup installations of various sizes.

The GALNET architecture relies on standard PCI bus technology as a high performance 1Gbps backbone, and uses Galileo's highly proprietary, patented switching technology, as well as industry standard Media Access Controllers. The GALNET architecture will over time include members of all the major local and wide area network technologies.

The GT-48001 Switched Ethernet Controller, the first chip using the GALNET architecture, contains a high-performance PCI Controller, a GALNET Protocol Controller, 8 Ethernet 10/20Mbps MACs with all digital logic, a high-performance Frame Controller, a powerful Switching Engine, a versatile DRAM Controller, and several key management features. The GT-48001 will cost $96 in moderate volumes, or $12 per port, making it the most cost-effective switched Ethernet solution in the market.P"The need for cost-effective high-performance solutions in the fast-growing switched networking market was the reason for creating the GALNET architecture, and the extraordinarily large installed base of 10Mbps adapter cards was the key motivator for designing the GT-48001 as the first family member", said Manuel Alba, President of Galileo Technology. "Most Ethernet installations possess a vast amount of untapped bandwidth due to their use as half duplex shared environments, which do not address the pressing need for more bandwidth by users of demanding applications like multimedia, engineering/scientific, and client-server computing. Galileo will enable switch vendors to provide economical dedicated 20Mbps links to satisfy this need, and in the near term will add 100/200Mbps members to the family".

First prototypes of the GT-48001 have been evaluated successfully by Galileo, and stress-testing is underway at several alpha sites.

How It Works

The GT-48001 uses a Store-and-Forward architecture and attains a forwarding rate of 650K Unicast packets per second, with very low last-bit-to-first-bit delay. Incoming packets go through the on-board MACs and the Frame Controller, which forwards them to the DRAM controller for temporary buffering in external DRAM, while the Switching Engine performs intelligent learning, address recognition and forwarding decisions. The packets are then sent to their destination, which in the simpler case may be another port in the same GT-48001. For other destinations, the packets travel over the PCI bus using the GALNET protocol, reaching another GT-48001 in the system, another network interface in the system, or the managing processor.

A switched Ethernet system can use as many as 32 GT-48001's, for a total of 256 10/20Mbps ports, with guaranteed filtering and forwarding at full wire speed in full duplex mode in all ports.

The GT-48001 has a comprehensive set of management features and a simple interface to the main processor, facilitating its use in heavily managed switches that cost tens of thousands of dollars. Similarly, mid-range equipment using the GT-48001 can offer very high quality management at very reasonable prices. Most interestingly perhaps is its use in low-end volume systems, since the GT-48001's self-learning mode allows it to operate without a processor. At present, equipment in these three categories is being designed by customers committed to the GALNET architecture.

The Key Blocks

The key elements of the GT-48001 are Galileo's proprietary Switching Engine and its Address Recognition mechanism, which can self-learn up to 8K Unicast addresses and unlimited Multicast/Broadcast addresses, while guaranteeing full wire speed without the need for expensive CAMs, SRAMs or similar components.

In order to attain a low system cost, the GT-48001 relies on low cost DRAM to store the address tables, as well as to buffer incoming packets. A high-performance DRAM controller for 1MByte or 2MBytes of standard or EDO DRAM is included on-chip. Packet buffers are dynamically allocated to the 8 ports and the PCI bus.

Eight 10/20Mbps serial interfaces are included on-chip, each with a production-proven Ethernet MAC, Manchester encoder/decoder, link integrity, auto-polarity, dual 32-Byte FIFOs, clock recovery, and support for 7 LEDs. Each of the 8 ports can be individually set to one of four modes: 10baseT, AUI, 10baseF, or NRZ Synchronous. Less than $2 of external electronics per port are needed to interface to 10baseT. The GT-48001 takes advantage of most of the theoretical 1Gbps PCI bandwidth by virtue of its elegant, innovative, and efficient architecture. It is compliant with version 2.1 of the standard, and it can operate as a master or as a slave. Galileo's unique GALNET protocol is the fabric that keeps the GALNET architecture together, and it consists of very simple messages over the PCI bus that allow all devices to communicate with each other for global address table updates, multicast and broadcast packet disposition, connectivity to other family members, and many other functions .

Several management features are part of the GT-48001. The processor has complete access to the address table and all the management bits contained in it, including bits for aging and static addresses. Hooks are provided for Spanning Tree, as well as for RMON. For statistics gathering, a full MIB is maintained per port, and counters are also kept for the PCI bus traffic. One of the 8 ports can behave as a Sniffer port for monitoring.

Finally, the GT-48001 features the powerful Intervention Mode, in which by setting a bit for an address table entry, various CPU intervention modes are enabled, which can greatly facilitate the implementation of routing decisions and other advanced features.

Design Aids

Galileo has designed the Galileo-6 Validation board as a simple PCI card with one GT-48001 and eight 10baseT ports. Galileo has entered into an agreement with Intel Corporation in which Intel will provide a complete reference design based on the i960( microprocessor family, using three GT-48001's in a 24-port switch.

Price, Support and Availability

The GT-48001 is packaged in a low-cost 208-pin PQFP, and samples can be ordered for early April delivery. Pricing for the GT-48001 is $96 for 10,000 pieces.

About Galileo Technology

Galileo Technology is a 3 year old fabless semiconductor company that designs and markets complex semiconductor devices which solve important problems in high-performance embedded control systems, principally in the area of data communications. Galileo's products are divided into three areas: high-performance core logic, data communications controllers, and application-specific memory (ASM) buffers. Galileo Technology has 45 employees, with technical headquarters located in Karmiel, Israel, and business headquarters located in San Jose, California.

i960 is a registered trademark of Intel Corporation.