ATM-TC Co-Processor

The physical layer in the ATM reference model consists of Physical Medium Dependent (PMD) and Transmission Convergence (TC) sub-layers. The ATM-TC co-processor engine implements the TC sub-layer and is independent of the bit timing and line coding aspects of the PMD and the physical interface standards. The co-processor provides host CPU offload for the following two functions: ATM Cell Transmitter and ATM Cell Receiver.

Key Features

The ATM-TC co-processor engine supports ATM cell interfaces as defined in ITU-T I.432.1 and I.432.3:

• Cell delineation
• Header Error Check (HEC) generation and insertion
• Octet level (byte aligned) and bit level operation
• User traffic screening based on matching header values
• Performance of single-bit HEC correction and single-bit or multiple-bit detection
• Provision of cell status, cell counts and error counts
• Insertion and filtering of idle cells
• Payload scrambling and de-scrambling

Counters:

• Loss of Cell Delineation (LOCD) events
• Corrected HEC errors
• Uncorrected HEC errors
• Transmitted cells
• Matching received cells
• Non-matching received cells

Configuration parameters:

• Idle cell header and payload
• Matching cell headers
• Scrambling
• HEC checking and correction