DesignCon 2026

Marvell at DesignCon 2026

DesignCon is the premier high-speed communications and system design conference and exposition, offering industry-critical engineering education in the heart of electronics innovation in Silicon Valley. It is the place for chip, board and systems design engineers to source, network and stay ahead of industry change.

Visit booth 904 in Exhibit Halls A-D to learn about the latest Marvell semiconductor and connectivity technologies that will redefine tomorrow’s AI infrastructure.

Marvell Presentations

Panel: The Case of the Closing Eyes: 200G/Lane (and pp) AI Hardware Dogfight Is Still Escalating — The Impact on You, Ethernet, NVLink, OIF, UEC and IB

Date/Time: Tuesday, February 24, 2026
Time: 4:45 – 6:00 PM
Location: Ballroom C
Marvell Speaker: Mike Dudek, Distinguished Engineer 

Presentation: IBIS-AMI Modeling for Bi-directional D2D Links with Clock Forwarding & Echo Cancellation
Date/Time: Wednesday, February 25, 2026
Time: 2:00 – 2:45 PM
Location: Ballroom E
Marvell Speakers:

• Foad Arvani, Principal Engineer
• Matthew Kelly, Principal Engineer
• John Ma, Senior Director
• Reza Nejad, Senior Staff Engineer
• Steven Parker, Senior Staff Manager – Architecture DSP
• Shaham Sharifian, Principal Engineer
• Davide Visani, Director – DSP Architecture

Presentation 448G Package Interconnects Design
Date/Time: Wednesday, February 25, 2026
Time: 2:00 – 2:45 PM
Location: Ballroom D
Marvell Speakers:

• Amir Askarian, Senior Staff Engineer
• Roberto Coccioli, Senior Distinguished Engineer
• Moutasem Eltawil, Senior Principal Engineer
• Chander Ravva, Senior Director
• Jamal Riani, Fellow
• Xiangrui Su, Staff Engineer
• Hugues Tournier, Senior Staff Manager
• Meenakshi Upadhyaya, Senior Manager
• Fu Yang, Distinguished Architect
• Wei Zhang, Senior Staff Engineer

Presentation Evaluation of 224G-PAM4 Co-Packaged Copper Interconnects for Next-Generation Ethernet
Date/Time: Thursday, February 26, 2026
Time: 11:15 AM – 12:00 PM
Location: Ballroom A
Marvell Speakers: Jie Lin, Principal System Engineer

Title: Scaling to 100+ Tb/s Switches Using Co-Packaged Connectors (CPC)
Date/Time: Thursday, February 26, 2026
Time: 12:15 – 1:00 PM 
Location: Ballroom C
Marvell Speakers:

• Roberto Coccioli, Senior Distinguished Engineer
• Lenin Patra, SVP – Technology
• Sina Shahi, Principal Engineer – DSP Architecture
• Kapil Shrikhande, Distinguished Engineer – Switch Architecture
• Davide Visani, Director – DSP Architecture