Archive for the 'Data Center' Category
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August 04, 2026
Marvell Structera™ X, A and S: A Comprehensive CXL Portfolio Powering AI Memory Innovation
By Khurram Malik, AVP, Data Center Memory and Storage Solutions, Marvell
CXL has become one of the most important technologies shaping AI infrastructure. As hyperscalers race to deploy larger AI models, longer context windows and increasingly memory-intensive inference workloads, memory capacity and bandwidth have emerged as critical constraints on performance, efficiency and scaling. At the same time, CXL adoption is reaching an inflection point, moving from evaluation into real-world deployment across hyperscale environments.
Marvell is leading this transition with Structera™ X memory expansion solutions developed alongside the world’s leading hyperscalers. The story begins with the shipping of Structera X 2404 and 2504 platforms, which have enabled hyperscalers to expand memory resources more efficiently, including extending the useful life of existing DDR4 investments while powering demanding AI workloads.
Structera X is not a series of disconnected product eras—it is a single, continuous architectural evolution. Today’s generation is already delivering real hyperscaler deployments, ecosystem maturity and a compelling TCO advantage. From that foundation, Marvell is extending the architecture toward the next phase of AI infrastructure innovation, adding capabilities enabled by the evolving CXL 3.2 ecosystem, PCIe Gen 6 connectivity and more advanced multi-host memory sharing architectures. These advancements will create larger, more flexible memory pools, enabling more efficient sharing of resources across servers and improving infrastructure utilization at hyperscale. As the architecture advances, Marvell is driving it toward higher bandwidth, deeper data optimization and increasingly disaggregated memory environments built to meet the growing demands of AI workloads.
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August 04, 2026
Photonic Fabric™ Technology: How Optical Connectivity Enables the Next Generation of AI Infrastructure
By Ravi Mahatme, Senior Director, Product Management, Photonic Fabric Business Unit, Marvell
AI infrastructure is entering a new architectural era. As AI inference scales, performance increasingly depends not simply on adding more compute, but on how efficiently compute, memory and connectivity operate together as one unified AI infrastructure system. Modern AI inference workloads are insatiable consumers of memory. Large language models, reasoning models and agentic AI applications require rapid access to model parameters, embeddings and rapidly growing key-value (KV) caches that preserve conversational context. These working data sets are growing into the hundreds of gigabytes, and increasingly terabytes, making memory capacity, bandwidth and latency just as important as accelerator performance. As AI infrastructure scales, overall system performance increasingly depends on how efficiently accelerators can access, move and utilize memory resources rather than simply adding more compute.
Why AI Needs a New Memory Tier
Today's AI memory hierarchy was never designed for inference at the scale modern workloads demand. High bandwidth memory (HBM) attached directly to GPUs delivers exceptional performance but remains expensive and capacity constrained. System DRAM provides larger memory pools but cannot economically scale alongside every accelerator. NVMe SSDs offer abundant capacity, yet their latency makes them unsuitable for serving active inference workloads.
This challenge is especially visible in large language models, where growing KV caches must remain readily accessible to avoid repeatedly recomputing previous tokens. Keeping these caches entirely in HBM is prohibitively expensive, while moving them to storage introduces latency that reduces token generation performance. The result is that GPUs increasingly spend valuable cycles waiting for data rather than performing inference.
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July 28, 2026
Performance, Connectivity and Programmability: How Teralynx T100 Sets a New Standard in AI Networking
By Rajagopal Krishnaswamy, Associate Vice President, Marvell
What do customers want from next-generation AI networks? Everything.
AI networks will need to manage exponentially more data across a rapidly expanding number of endpoints and evolving topologies, while reducing both cost and energy per bit. And, with data spending more than 30% of the time inside networks during training,1 congestion, transmission errors and other problems need to be kept to a minimum.
These networks will also need to be able to scale rapidly: AI networking spending is expected to reach $81.3 billion by 2030, more than 10x 2025 levels.2
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July 08, 2026
Scaling AI Networks with Intelligent Ethernet: Validating Packet Trimming, Auto Load Balancing (ALB) and Ultra Ethernet Transport (UET) on Marvell Teralynx
By Vikram Dattatri, Senior Engineer, Cloud Platform Group, Marvell
Packet trimming doesn’t prevent traffic losses from occurring; instead, it streamlines the process for recovering them. It is also one of many technologies Marvell is developing to optimize networks for the AI era.
Artificial intelligence infrastructure is driving a fundamental shift in how data center networks are designed, validated, and deployed. As clusters scale to thousands—or even tens of thousands—of GPUs, the network is no longer just a connectivity layer. It becomes a tightly coupled component of the compute system, directly impacting job completion time, efficiency and overall cost.
To address these evolving requirements, Ethernet is undergoing a transformation. At OFC 2026, Marvell and Keysight Technologies demonstrated (see the video below) how next-generation Ethernet fabrics can meet the demands of AI workloads through a combination of advanced features and realistic validation. Leveraging Keysight’s KAI Data Center Builder and AresONE‑M 800GE platform, the collaboration showcased how the Marvell® Teralynx® switch fabric supports emerging Ultra Ethernet Consortium (UEC) capabilities, with a particular focus on packet trimming, Auto Load Balancing (ALB) and Ultra Ethernet Transport (UET).
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June 24, 2026
Structera X and A CXL Compression: Making Every Gigabyte Count
By Arifur Rahman, Director of Product Marketing, Custom Cloud Solutions, Marvell
Modern AI workloads are insatiable consumers of memory. Deep learning recommendation models (DLRM), large language model (LLM) inference, in-memory databases and vector search engines all share a common bottleneck: there is never enough DRAM, and what exists is very expensive.
At today's spot prices—$27–$37 per GB for server-grade DDR5 RDIMMs1—a 12TB memory pool requires nearly half a million dollars in DRAM alone. Meanwhile, AI infrastructure buildouts are consuming server DRAM capacity faster than fabs can produce it, driving prices up 300–400% since mid-2025.1, 2
CXL memory expansion was supposed to solve this. And it does—but there's a subtler lever that most solutions ignore: the data sitting in that memory is compressible, and most CXL controllers don't touch it.
Recent Posts
- Marvell Structera™ X, A and S: A Comprehensive CXL Portfolio Powering AI Memory Innovation
- Powering the Next Generation of PCIe Gen6 NVMe SSDs with the Marvell® Bravera™ SC6 SSD Controller
- Photonic Fabric™ Technology: How Optical Connectivity Enables the Next Generation of AI Infrastructure
- The Marvell Internship Experience: Voices from the Program
- Performance, Connectivity and Programmability: How Teralynx T100 Sets a New Standard in AI Networking
