Latest Marvell Blog Articles
-
June 24, 2026
Structera X and A CXL Compression: Making Every Gigabyte Count
By Arifur Rahman, Director of Product Marketing, Custom Cloud Solutions, Marvell
Modern AI workloads are insatiable consumers of memory. Deep learning recommendation models (DLRM), large language model (LLM) inference, in-memory databases and vector search engines all share a common bottleneck: there is never enough DRAM, and what exists is very expensive.
At today's spot prices—$27–$37 per GB for server-grade DDR5 RDIMMs1—a 12TB memory pool requires nearly half a million dollars in DRAM alone. Meanwhile, AI infrastructure buildouts are consuming server DRAM capacity faster than fabs can produce it, driving prices up 300–400% since mid-2025.1, 2
CXL memory expansion was supposed to solve this. And it does—but there's a subtler lever that most solutions ignore: the data sitting in that memory is compressible, and most CXL controllers don't touch it.
-
June 17, 2026
Plasmonics: A Path to Higher Bandwidth in Optics in the AI Era
By Claudia Hoessbacher, Senior Director, and Wolfgang Heni, Director, Optical Engineering, Marvell
Plasmons have been used to accelerate drug discovery, enhance the sensitivity of sensors and even create artistic treasures in the Roman era.
Ongoing research at Marvell seeks to harness them to improve the performance of optical networks for the AI era. Plasmonics, a technology that leverages the properties of surface plasmon polaritons (SPPs), provides a promising pathway for enhancing the roadmap of silicon photonic (SiPho) light engines, a critical component inside optical modules.
Plasmonic-based SiPho light engines could support modules operating at 3.2T and beyond while consuming a fraction of the space and power per bit of modules based on existing technologies. Manufacturers could leverage foundry process technologies for scaling production.
-
May 28, 2026
Open CPX Sets the Stage for More Flexible, Scalable Connectivity
By George Hervey, Associate Vice President, Cloud Switch Marketing, Marvell
Co-packaged connectivity is coming. The Open CPX MSA (Co-packaging Multisource Agreement) is working to simplify adoption.
The consortium, which includes Marvell and other leaders in connectivity, is developing specifications and standards for solutions for integrating near-packaged optical (NPO) and/or co-packaged optical (CPO) technology into switches and servers in scalable, repeatable ways. Members are also working to support interoperability with co-packaged copper (CPC).
The idea is to give data center service providers, equipment manufacturers and others a unified framework for next-generation connectivity to accelerate innovation and meet the surging demand for these technologies. Fewer than one million near- and co-packaged ports shipped in 2025, according to LightCounting; by 2030, shipments are projected to surpass 100 million ports per year.1 Standards that can ensure predictability and flexibility will be critical in enabling this expected growth.
“The initial target of the MSA will be to develop an optimized optical engine with a defined pluggable socket and electrical connector system supporting high speed and high-density connectivity between a switch or processor and co-packaged and near-package interconnects,” the Open CPX MSA website states. “The specifications will define connector mechanicals, thermals, electrical pinout, mechanical form factors, electrical, optical, and management interface specifications to ensure interoperability between multiple vendors of Open CPX.”
-
May 26, 2026
224G Long-Range SerDes for Scale-up and Scale-inside
By Aatreya Chakravarti, Senior Staff Engineer, Custom Cloud Solutions, Marvell
In dense computing environments, copper continues to surprise.
Luxshare-Tech and Marvell teamed up on a compelling demonstration at OFC 2026 highlighting how long-reach serializer/deserializer (LR SerDes) technology can be integrated with co-packaged copper (CPC) and other connectivity solutions to create high-performance, high-bandwidth scale-inside fabrics for linking chips within server or switch trays or scale-up or scale-out networks linking trays within a rack. In other words, connections that can traverse an entire rack with low bit error rates (BER) that minimize power, cost, volumetric space and component count.
The demo is based on a Marvell 3nm 224G LR SerDes driving signals across a CPC-Backplane-CPC channel composed of a 0.75-meter, thin-gauge (31 AWG) KOOLIO™CPC solution from Luxshare-Tech, a 1-meter Luxshare-Tech Intrepid™ APEX backplane solution (26 AWG) and another 0.75-meter KOOLIO™ CPC solution for a cumulative transmission distance of 2.5 meters. Data gets transmitted across eight SerDes lanes. End-to-end bump losses come to 48dB with lane BERs reaching 1e-11, far lower than the specification.1 The video has more:
-
May 21, 2026
PCIe-based Switching for AI Scale-up Networks
By Krishna Mallampati, Senior Director of Product Marketing, Data Center Switching, Marvell
Peripheral Component Interconnect Express (PCIe)® is the world’s most popular interconnect for connections between chips in a shared system, while ensuring low latency, and it is well suited to be deployed for the scale-up domain. Scale-up networks extend across racks and possess hundreds of processors; low latency and high bandwidth are required in these systems that make up the foundation of AI data centers.
Marvell demonstrates the industry’s first 260-lane PCIe 6.0 switch in the video below, marking a new performance standard for PCIe scale-up performance—256 lanes of data traffic (plus four lanes for management) is the industry’s highest radix for a PCIe switch.
Traditional PCIe switch architectures require multiple devices to scale, racking up complexity and cost. However, the Marvell Structera S PCIe switch flattens the network and eliminates the need for multiple smaller switches in a large scale-up system. This enables higher density, lower latency and overall increased system efficiency, making it an optimal solution for hyperscale operators.
