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April 25, 2016

How Marvell FLC Redefines Main Memory

By Hunglin Hsu, Vice President, Digital IC Design, Marvell

With newer, bigger programs and more apps multitasking simultaneously, the answer to making any system run faster, from handheld to super computer, was always just to add more DRAM. . . and more, and more and more. Well, those days will soon be “memory” with Marvell’s introduction of Final-Level Cache™ (FLC™). FLC is an architecture that redefines memory on everything from data centers to wearables. By offloading the storage of programs to less expensive solid-state drives (SSDs) and only using a small amount of expensive DRAM to cache the active processes, the amount of DRAM can be cut dramatically along with power consumption.  FLC has the potential to spark the development of a new class of lower-cost and lower- power products and cut the DRAM needed in a system by as much as 10x, while cutting the energy consumed to about half what is used today. FLC-solution-003 How? If you look at what’s actually being used on your computer or portable device, only a small percentage of the application code loaded into the main memory is usually active. Take a look for yourself. For example, look at the process monitor in Windows task manager. You will see that most of the applications are idle, yet in aggregate require a significant amount of DRAM space. In fact, nearly 90 to 99 percent of most DRAMs are idle. By using a special algorithm, Marvell FLC can put the most frequently used programs on a small amount of DRAM and the rest onto less expensive, energy-efficient flash memory that can reduce the size, cost and power requirements of anything from a smart car, to mobile phones, tablets, smart watches, computers or data centers. 

And it works!  Our engineering mobile phone platform, shown in this video, uses FLC to play back video smoothly, without any lag or stutter.  App switching is also zippy.  Such performance is common on mid- or even high-end phones with large DRAM, yet this design used only 768MB of DRAM in the implementation.  Time-sensitive streams are mapped to a 512MB non-cacheable area, while another 256 DRAM is used in FLC to emulate 1GB of memory. Hence, it provides similar performance to 1.5GB of main memory in traditional DRAM-based designs. FLC can also emulate larger quantities of main memory.  The second proof of concept demonstrates smooth video performance on the same mobile phone platform using FLC. 

With FLC, better performance can be achieved by reporting to the operating system a larger than physically implemented main memory. The operating system is thus less likely to kill background apps, which is why the fast app switching is possible. The FLC hardware does all the heavy lifting in the background and frees up the tasks of the operating system.

Smaller DRAM means less power and lower cost creating endless new possibilities. It will free up innovation in digital design and even accelerate categories like the Internet of Things (IoT.)  By offloading storage to cheaper SSD memory, the world can also dramatically reduce overall power consumption and energy needs. For example, a 50 percent reduction in all computer energy use equates to a two percent decrease in rural power needs. Battery life of laptops will be increased, as well as IoT devices that could last weeks before recharging. It changes the future of supercomputers as well. With FLC, you can replace an entire server room with a small portable device. Super computing and computational sets will become faster and more efficient, with future super computers containing tens of terabytes of memory instead of hundreds of gigabytes. Data center space savings and cooling costs will also be dramatically reduced. 

This is why Marvell Final-Level Cache represents a monumental technical step forward. Marvell FLC will not only redefine memory--but all of computing. 

See Marvell FLC in action in the following proof of concept videos:

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