Marvell Blogs

Archive for the 'Cloud' Category

• August 04, 2026

  

  

  

  Photonic Fabric™ Technology: How Optical Connectivity Enables the Next Generation of AI Infrastructure

  By Ravi Mahatme, Senior Director, Product Management, Photonic Fabric Business Unit, Marvell

  AI infrastructure is entering a new architectural era. As AI inference scales, performance increasingly depends not simply on adding more compute, but on how efficiently compute, memory and connectivity operate together as one unified AI infrastructure system. Modern AI inference workloads are insatiable consumers of memory. Large language models, reasoning models and agentic AI applications require rapid access to model parameters, embeddings and rapidly growing key-value (KV) caches that preserve conversational context. These working data sets are growing into the hundreds of gigabytes, and increasingly terabytes, making memory capacity, bandwidth and latency just as important as accelerator performance. As AI infrastructure scales, overall system performance increasingly depends on how efficiently accelerators can access, move and utilize memory resources rather than simply adding more compute.

  Why AI Needs a New Memory Tier

  Today's AI memory hierarchy was never designed for inference at the scale modern workloads demand. High bandwidth memory (HBM) attached directly to GPUs delivers exceptional performance but remains expensive and capacity constrained. System DRAM provides larger memory pools but cannot economically scale alongside every accelerator. NVMe SSDs offer abundant capacity, yet their latency makes them unsuitable for serving active inference workloads.

  This challenge is especially visible in large language models, where growing KV caches must remain readily accessible to avoid repeatedly recomputing previous tokens. Keeping these caches entirely in HBM is prohibitively expensive, while moving them to storage introduces latency that reduces token generation performance. The result is that GPUs increasingly spend valuable cycles waiting for data rather than performing inference.

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• July 08, 2026

  

  

  

  Scaling AI Networks with Intelligent Ethernet: Validating Packet Trimming, Auto Load Balancing (ALB) and Ultra Ethernet Transport (UET) on Marvell Teralynx

  By Vikram Dattatri, Senior Engineer, Cloud Platform Group, Marvell

  Packet trimming doesn’t prevent traffic losses from occurring; instead, it streamlines the process for recovering them. It is also one of many technologies Marvell is developing to optimize networks for the AI era.

  Artificial intelligence infrastructure is driving a fundamental shift in how data center networks are designed, validated, and deployed. As clusters scale to thousands—or even tens of thousands—of GPUs, the network is no longer just a connectivity layer. It becomes a tightly coupled component of the compute system, directly impacting job completion time, efficiency and overall cost.

  To address these evolving requirements, Ethernet is undergoing a transformation. At OFC 2026, Marvell and Keysight Technologies demonstrated (see the video below) how next-generation Ethernet fabrics can meet the demands of AI workloads through a combination of advanced features and realistic validation. Leveraging Keysight’s KAI Data Center Builder and AresONE‑M 800GE platform, the collaboration showcased how the Marvell® Teralynx® switch fabric supports emerging Ultra Ethernet Consortium (UEC) capabilities, with a particular focus on packet trimming, Auto Load Balancing (ALB) and Ultra Ethernet Transport (UET).

   

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• June 24, 2026

  

  

  

  Structera X and A CXL Compression: Making Every Gigabyte Count

  By Arifur Rahman, Director of Product Marketing, Custom Cloud Solutions, Marvell

  

  Modern AI workloads are insatiable consumers of memory. Deep learning recommendation models (DLRM), large language model (LLM) inference, in-memory databases and vector search engines all share a common bottleneck: there is never enough DRAM, and what exists is very expensive.

  At today's spot prices—$27–$37 per GB for server-grade DDR5 RDIMMs1—a 12TB memory pool requires nearly half a million dollars in DRAM alone. Meanwhile, AI infrastructure buildouts are consuming server DRAM capacity faster than fabs can produce it, driving prices up 300–400% since mid-2025.^{1, 2}

  CXL memory expansion was supposed to solve this. And it does—but there's a subtler lever that most solutions ignore: the data sitting in that memory is compressible, and most CXL controllers don't touch it.

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• June 17, 2026

  

  

  

  Plasmonics: A Path to Higher Bandwidth in Optics in the AI Era

  By Claudia Hoessbacher, Senior Director, and Wolfgang Heni, Director, Optical Engineering, Marvell

  Plasmons have been used to accelerate drug discovery, enhance the sensitivity of sensors and even create artistic treasures in the Roman era.

  Ongoing research at Marvell seeks to harness them to improve the performance of optical networks for the AI era. Plasmonics, a technology that leverages the properties of surface plasmon polaritons (SPPs), provides a promising pathway for enhancing the roadmap of silicon photonic (SiPho) light engines, a critical component inside optical modules.

  Plasmonic-based SiPho light engines could support modules operating at 3.2T and beyond while consuming a fraction of the space and power per bit of modules based on existing technologies. Manufacturers could leverage foundry process technologies for scaling production.

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• May 28, 2026

  

  

  

  Open CPX Sets the Stage for More Flexible, Scalable Connectivity

  By George Hervey, Associate Vice President, Cloud Switch Marketing, Marvell

  Co-packaged connectivity is coming. The Open CPX MSA (Co-packaging Multisource Agreement) is working to simplify adoption.

  The consortium, which includes Marvell and other leaders in connectivity, is developing specifications and standards for solutions for integrating near-packaged optical (NPO) and/or co-packaged optical (CPO) technology into switches and servers in scalable, repeatable ways. Members are also working to support interoperability with co-packaged copper (CPC).

  The idea is to give data center service providers, equipment manufacturers and others a unified framework for next-generation connectivity to accelerate innovation and meet the surging demand for these technologies. Fewer than one million near- and co-packaged ports shipped in 2025, according to LightCounting; by 2030, shipments are projected to surpass 100 million ports per year.¹ Standards that can ensure predictability and flexibility will be critical in enabling this expected growth.

  “The initial target of the MSA will be to develop an optimized optical engine with a defined pluggable socket and electrical connector system supporting high speed and high-density connectivity between a switch or processor and co-packaged and near-package interconnects,” the Open CPX MSA website states. “The specifications will define connector mechanicals, thermals, electrical pinout, mechanical form factors, electrical, optical, and management interface specifications to ensure interoperability between multiple vendors of Open CPX.”

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Recent Posts

• Marvell® Photonic Fabric™ Wins AI Infrastructure Award at FMS 2026
• Accelerating AI Infrastructure with Marvell Structera A and SK hynix CXL Memory: Enabling Efficient Near-Memory Processing
• Marvell Structera™ X, A and S: A Comprehensive CXL Portfolio Powering AI Memory Innovation
• Powering the Next Generation of PCIe Gen6 NVMe SSDs with the Marvell® Bravera™ SC6 SSD Controller
• Photonic Fabric™ Technology: How Optical Connectivity Enables the Next Generation of AI Infrastructure